shithub: riscv

Download patch

ref: f4b6320240a30144af217128eae886a531d9e78c
parent: 4cd46e8601a04d2dc4fa91f95f5be4be14943c96
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Thu Apr 17 18:35:01 EDT 2025 

kernel: explicitely pass MiiPhy* to ethermii operations

The Mii.curphy pointer is just a convenient shorthand
that points to the first enumerated phy found by mii().

If multiple phy's are in use on a single mdio bus,
we want the interface to not depend on Mii.curphy.

This also simplifies the code for most operations,
as curphy checking can be avoided.

All clause22 accesses now pass thru miimir()/miimiw()
(except when enumerating). Which allows us to put some
serialization there later.


--- a/sys/src/9/bcm64/ethergenet.c
+++ b/sys/src/9/bcm64/ethergenet.c
@@ -723,16 +723,16 @@
 }
 
 static int
-bcmshdr(Mii *mii, int reg)
+bcmshdr(MiiPhy *phy, int reg)
 {
-	miimiw(mii, 0x1C, (reg & 0x1F) << 10);
-	return miimir(mii, 0x1C) & 0x3FF;
+	miimiw(phy, 0x1C, (reg & 0x1F) << 10);
+	return miimir(phy, 0x1C) & 0x3FF;
 }
 
 static int
-bcmshdw(Mii *mii, int reg, int dat)
+bcmshdw(MiiPhy *phy, int reg, int dat)
 {
-	return miimiw(mii, 0x1C, 0x8000 | (reg & 0x1F) << 10 | (dat & 0x3FF));
+	return miimiw(phy, 0x1C, 0x8000 | (reg & 0x1F) << 10 | (dat & 0x3FF));
 }
 
 static int
@@ -756,10 +756,12 @@
 
 	for(;;){
 		tsleep(ctlr->link, linkevent, ctlr, 1000);
-		miistatus(ctlr->mii);
 		phy = ctlr->mii->curphy;
-		if(phy == nil || phy->link == link)
+		if(phy == nil)
 			continue;
+		miistatus(phy);
+		if(phy->link == link)
+			continue;
 		link = phy->link;
 		if(link){
 			u32int cmd = CmdRxEn|CmdTxEn;
@@ -824,6 +826,7 @@
 attach(Ether *edev)
 {
 	Ctlr *ctlr = edev->ctlr;
+	MiiPhy *phy;
 
 	eqlock(ctlr);
 	if(ctlr->attached){
@@ -874,36 +877,35 @@
 	ctlr->mii->mir = mdior;
 	ctlr->mii->miw = mdiow;
 	mii(ctlr->mii, ~0);
-
-	if(ctlr->mii->curphy == nil)
+	phy = ctlr->mii->curphy;
+	if(phy == nil)
 		error("no phy");
 
 	print("#l%d: phy%d id %.8ux oui %x\n", 
-		edev->ctlrno, ctlr->mii->curphy->phyno, 
-		ctlr->mii->curphy->id, ctlr->mii->curphy->oui);
+		edev->ctlrno, phy->phyno, phy->id, phy->oui);
 
-	miireset(ctlr->mii);
+	miireset(phy);
 
-	switch(ctlr->mii->curphy->id){
+	switch(phy->id){
 	case 0x600d84a2:	/* BCM54312PE */
 		/* mask interrupts */
-		miimiw(ctlr->mii, 0x10, miimir(ctlr->mii, 0x10) | 0x1000);
+		miimiw(phy, 0x10, miimir(phy, 0x10) | 0x1000);
 
 		/* SCR3: clear DLLAPD_DIS */
-		bcmshdw(ctlr->mii, 0x05, bcmshdr(ctlr->mii, 0x05) &~0x0002);
+		bcmshdw(phy, 0x05, bcmshdr(phy, 0x05) &~0x0002);
 		/* APD: set APD_EN */
-		bcmshdw(ctlr->mii, 0x0a, bcmshdr(ctlr->mii, 0x0a) | 0x0020);
+		bcmshdw(phy, 0x0a, bcmshdr(phy, 0x0a) | 0x0020);
 
 		/* blinkenlights */
-		bcmshdw(ctlr->mii, 0x09, bcmshdr(ctlr->mii, 0x09) | 0x0010);
-		bcmshdw(ctlr->mii, 0x0d, 3<<0 | 0<<4);
+		bcmshdw(phy, 0x09, bcmshdr(phy, 0x09) | 0x0010);
+		bcmshdw(phy, 0x0d, 3<<0 | 0<<4);
 		break;
 	}
 
 	/* don't advertise EEE */
-	miimmdw(ctlr->mii, 7, 60, 0);
+	miimmdw(phy, 7, 60, 0);
 
-	miiane(ctlr->mii, ~0, AnaAP|AnaP, ~0);
+	miiane(phy, ~0, AnaAP|AnaP, ~0);
 
 	ctlr->attached = 1;
 
--- a/sys/src/9/imx8/etherimx.c
+++ b/sys/src/9/imx8/etherimx.c
@@ -473,10 +473,10 @@
 
 	while(waserror())
 		;
-	miiane(ctlr->mii, ~0, ~0, ~0);
+	phy = ctlr->mii->curphy;
+	miiane(phy, ~0, ~0, ~0);
 	for(;;){
-		miistatus(ctlr->mii);
-		phy = ctlr->mii->curphy;
+		miistatus(phy);
 		if(phy->link == link){
 			tsleep(ctlr->mii, return0, nil, 5000);
 			continue;
--- a/sys/src/9/imx8/mkfile
+++ b/sys/src/9/imx8/mkfile
@@ -103,7 +103,7 @@
 pciimx.$O: ../port/pci.h
 usbxhciimx.$O: ../port/usbxhci.h ../port/usb.h
 usdhc.$O: ../port/sd.h
-etherimx.$O: ../port/netif.h ../port/etherif.h
+etherimx.$O: ../port/netif.h ../port/etherif.h ../port/ethermii.h
 
 l.$O main.$O clock.$O gic.$O cache.v8.$O fpu.$O trap.$O rebootcode.$O: ../arm64/sysreg.h
 
--- a/sys/src/9/kw/ether1116.c
+++ b/sys/src/9/kw/ether1116.c
@@ -1096,12 +1096,13 @@
  * on openrd, ether0's phy has address 8, ether1's is ether0's 24.
  * on guruplug, ether0's is phy 0 and ether1's is ether0's phy 1.
  */
-int
-mymii(Mii* mii, int mask)
+uint
+mymii(Mii* mii, uint mask)
 {
 	Ctlr *ctlr;
-	MiiPhy *miiphy;
-	int bit, ctlrno, oui, model, phyno, r, rmask;
+	MiiPhy *phy;
+	int ctlrno, oui, model, phyno, r;
+	uint bit, rmask;
 	static int dualport, phyidx;
 	static int phynos[NMiiPhy];
 
@@ -1112,7 +1113,7 @@
 	dualport = 0;
 	if (ctlrno == 0) {
 		for(phyno = 0; phyno < NMiiPhy; phyno++){
-			bit = 1<<phyno;
+			bit = 1U<<phyno;
 			if(!(mask & bit) || mii->mask & bit)
 				continue;
 			if(mii->mir(mii, phyno, Bmsr) == -1)
@@ -1151,11 +1152,11 @@
 		MIIDBG("ctlrno %d using ctlrno 0's phyno %d\n",
 			ctlrno, phynos[ctlrno]);
 		ctlr->mii = mii = ctlrs[0]->mii;
-		mask = 1 << phynos[ctlrno];
+		mask = 1U << phynos[ctlrno];
 		mii->mask = ~mask;
 	}
 	for(phyno = 0; phyno < NMiiPhy; phyno++){
-		bit = 1<<phyno;
+		bit = 1U<<phyno;
 		if(!(mask & bit))
 			continue;
 		if(mii->mask & bit){
@@ -1171,19 +1172,19 @@
 		if(oui == 0xFFFFF || oui == 0)
 			continue;
 
-		if((miiphy = malloc(sizeof(MiiPhy))) == nil)
+		if((phy = malloc(sizeof(MiiPhy))) == nil)
 			continue;
-		miiphy->mii = mii;
-		miiphy->oui = oui;
-		miiphy->phyno = phyno;
+		phy->mii = mii;
+		phy->oui = oui;
+		phy->phyno = phyno;
 
-		miiphy->anar = ~0;
-		miiphy->fc = ~0;
-		miiphy->mscr = ~0;
+		phy->anar = ~0;
+		phy->fc = ~0;
+		phy->mscr = ~0;
 
-		mii->phy[phyno] = miiphy;
+		mii->phy[phyno] = phy;
 		if(ctlrno == 0 || hackflavour != Hackdual && mii->curphy == nil)
-			mii->curphy = miiphy;
+			mii->curphy = phy;
 		mii->mask |= bit;
 		mii->nphy++;
 
@@ -1218,26 +1219,26 @@
 	MIIDBG("oui %#X phyno %d\n", phy->oui, phy->phyno);
 	// TODO: does this make sense? shouldn't each phy be initialised?
 	if((ctlr->ether->ctlrno == 0 || hackflavour != Hackdual) &&
-	    miistatus(ctlr->mii) < 0){
-		miireset(ctlr->mii);
+	    miistatus(phy) < 0){
+		miireset(phy);
 		MIIDBG("miireset\n");
-		if(miiane(ctlr->mii, ~0, 0, ~0) < 0){
+		if(miiane(phy, ~0, 0, ~0) < 0){
 			iprint("miiane failed\n");
 			return -1;
 		}
 		MIIDBG("miistatus\n");
-		miistatus(ctlr->mii);
-		if(miird(ctlr->mii, phy->phyno, Bmsr) & BmsrLs){
+		miistatus(phy);
+		if(miimir(phy, Bmsr) & BmsrLs){
 			for(i = 0; ; i++){
 				if(i > 600){
 					iprint("ether1116: autonegotiation failed\n");
 					break;
 				}
-				if(miird(ctlr->mii, phy->phyno, Bmsr) & BmsrAnc)
+				if(miimir(phy, Bmsr) & BmsrAnc)
 					break;
 				delay(10);
 			}
-			if(miistatus(ctlr->mii) < 0)
+			if(miistatus(phy) < 0)
 				iprint("miistatus failed\n");
 		}else{
 			iprint("ether1116: no link\n");
@@ -1290,12 +1291,12 @@
 	miiregpage(mii, dev, Pagrgmii);
 	miiwr(mii, dev, Scr, miird(mii, dev, Scr) | Rgmiipwrup);
 	/* must now do a software reset, says the manual */
-	miireset(ctlr->mii);
+	miireset(mii->curphy);
 
 	/* enable RGMII delay on Tx and Rx for CPU port */
 	miiwr(mii, dev, Recr, miird(mii, dev, Recr) | Rxtiming | Rxtiming);
 	/* must now do a software reset, says the manual */
-	miireset(ctlr->mii);
+	miireset(mii->curphy);
 
 	miiregpage(mii, dev, Pagcopper);
 	miiwr(mii, dev, Scr,
--- a/sys/src/9/mt7688/ether7688.c
+++ b/sys/src/9/mt7688/ether7688.c
@@ -562,9 +562,9 @@
 		edev->ctlrno, ctlr->mii->curphy->phyno, 
 		ctlr->mii->curphy->id, ctlr->mii->curphy->oui);
 
-	miireset(ctlr->mii);
+	miireset(ctlr->mii->curphy);
 
-	miiane(ctlr->mii, ~0, ~0, ~0);
+	miiane(ctlr->mii->curphy, ~0, ~0, ~0);
 
 	return 0;
 }
--- a/sys/src/9/pc/ether8169.c
+++ b/sys/src/9/pc/ether8169.c
@@ -427,18 +427,17 @@
 		rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);	/* magic */
 	}
 
-	if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
+	if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil)
 		error("no phy");
-	}
 
 	print("#l%d: rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 		edev->ctlrno, phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 
-	miireset(ctlr->mii);
+	miireset(phy);
 
 	microdelay(100);
 
-	miiane(ctlr->mii, ~0, ~0, ~0);
+	miiane(phy, ~0, ~0, ~0);
 }
 
 static void
@@ -596,7 +595,7 @@
 		for(i = 0; i < NMiiPhyr; i++){
 			if(i && ((i & 0x07) == 0))
 				p = seprint(p, e, "\n       ");
-			r = miimir(ctlr->mii, i);
+			r = miimir(ctlr->mii->curphy, i);
 			p = seprint(p, e, " %4.4ux", r);
 		}
 		p = seprint(p, e, "\n");
--- a/sys/src/9/pc/etherdp83820.c
+++ b/sys/src/9/pc/etherdp83820.c
@@ -921,7 +921,7 @@
 		for(i = 0; i < NMiiPhyr; i++){
 			if(i && ((i & 0x07) == 0))
 				p = seprint(p, e, "\n    ");
-			r = miimir(ctlr->mii, i);
+			r = miimir(ctlr->mii->curphy, i);
 			p = seprint(p, e, " %4.4uX", r);
 		}
 		p = seprint(p, e, "\n");
--- a/sys/src/9/pc/etheri225.c
+++ b/sys/src/9/pc/etheri225.c
@@ -548,6 +548,7 @@
 {
 	u32int r;
 	u32int rt;
+	MiiPhy *phy;
 
 	/* acquire control of the phy */
 	if (i225synclock(c, c->pdevfunc ? SMSphy1 : SMSphy0) < 0)
@@ -580,7 +581,7 @@
 	c->mii->ctlr = c;
 	c->mii->mir = i225miir;
 	c->mii->miw = i225miiw;
-	if (mii(c->mii, ~0) == 0) {
+	if (mii(c->mii, ~0) == 0 || (phy = c->mii->curphy) == nil) {
 		free(c->mii); c->mii = nil;
 		error("phy");
 	}
@@ -587,8 +588,8 @@
 
 	/* configure for auto-negotiated link */
 	csr32w(c, Rdevctrl, csr32r(c, Rdevctrl) | DClink | DClinkauto);
-	miimiw(c->mii, Bmcr, miimir(c->mii, Bmcr) & ~BmcrPd); microdelay(300);
-	miiane(c->mii, ~0, ~0, ~0);
+	miimiw(phy, Bmcr, miimir(phy, Bmcr) & ~BmcrPd); microdelay(300);
+	miiane(phy, ~0, ~0, ~0);
 }
 
 static void
@@ -994,28 +995,27 @@
 i225proclink(void *a)
 {
 	Ctlr *c;
+	MiiPhy *phy;
 
 	c = a;
 	while (waserror())
 		;
-
 	/* process link status */
 	for (;; sleep(c, return0, nil)) {
-		miistatus(c->mii);
-		if (c->mii->curphy == nil) {
+		phy = c->mii->curphy;
+		if (phy == nil) {
 			/* phy missing? */
 			continue;
 		}
-
-		if (c->mii->curphy->speed == 0) {
+		miistatus(phy);
+		if (phy->speed == 0) {
 			/* phy errata: rinse and repeat, should only happen once */
-			miireset(c->mii);
+			miireset(phy);
 			continue;
 		}
-
 		/* report status */
-		ethersetspeed(c->edev, c->mii->curphy->speed);
-		ethersetlink(c->edev, c->mii->curphy->link);
+		ethersetspeed(c->edev, phy->speed);
+		ethersetlink(c->edev, phy->link);
 	}
 }
 
--- a/sys/src/9/pc/etherigbe.c
+++ b/sys/src/9/pc/etherigbe.c
@@ -655,7 +655,7 @@
 		for(i = 0; i < NMiiPhyr; i++){
 			if(i && ((i & 0x07) == 0))
 				p = seprint(p, e, "\n       ");
-			r = miimir(ctlr->mii, i);
+			r = miimir(ctlr->mii->curphy, i);
 			p = seprint(p, e, " %4.4uX", r);
 		}
 		p = seprint(p, e, "\n");
@@ -782,7 +782,7 @@
 	while(waserror())
 		;
 	for(;;){
-		if(ctlr->mii == nil || ctlr->mii->curphy == nil)
+		if(ctlr->mii == nil || (phy = ctlr->mii->curphy) == nil)
 			continue;
 
 		/*
@@ -793,11 +793,9 @@
 		 *
 		 *	MiiPhy.speed, etc. should be in Mii.
 		 */
-		if(miistatus(ctlr->mii) < 0)
-			//continue;
+		if(miistatus(phy) < 0)
 			goto enable;
 
-		phy = ctlr->mii->curphy;
 		ctrl = csr32r(ctlr, Ctrl);
 
 		switch(ctlr->id){
@@ -1483,7 +1481,6 @@
 		ctlr->mii = nil;
 		return -1;
 	}
-	USED(phy);
 	// print("oui %X phyno %d\n", phy->oui, phy->phyno);
 
 	/*
@@ -1504,25 +1501,25 @@
 	case i82546eb:
 		break;
 	default:
-		r = miimir(ctlr->mii, 16);
+		r = miimir(phy, 16);
 		r |= 0x0800;			/* assert CRS on Tx */
 		r |= 0x0060;			/* auto-crossover all speeds */
 		r |= 0x0002;			/* polarity reversal enabled */
-		miimiw(ctlr->mii, 16, r);
+		miimiw(phy, 16, r);
 
-		r = miimir(ctlr->mii, 20);
+		r = miimir(phy, 20);
 		r |= 0x0070;			/* +25MHz clock */
 		r &= ~0x0F00;
 		r |= 0x0100;			/* 1x downshift */
-		miimiw(ctlr->mii, 20, r);
+		miimiw(phy, 20, r);
 
-		miireset(ctlr->mii);
+		miireset(phy);
 		p = 0;
 		if(ctlr->txcw & TxcwPs)
 			p |= AnaP;
 		if(ctlr->txcw & TxcwAs)
 			p |= AnaAP;
-		miiane(ctlr->mii, ~0, p, ~0);
+		miiane(phy, ~0, p, ~0);
 		break;
 	}
 	return 0;
--- a/sys/src/9/pc/ethervt6102.c
+++ b/sys/src/9/pc/ethervt6102.c
@@ -377,7 +377,7 @@
 		for(i = 0; i < NMiiPhyr; i++){
 			if(i && ((i & 0x07) == 0))
 				p = seprint(p, e, "\n       ");
-			r = miimir(ctlr->mii, i);
+			r = miimir(ctlr->mii->curphy, i);
 			p = seprint(p, e, " %4.4uX", r);
 		}
 		p = seprint(p, e, "\n");
@@ -442,12 +442,10 @@
 	while(waserror())
 		;
 	for(;;){
-		if(ctlr->mii == nil || ctlr->mii->curphy == nil)
+		if(ctlr->mii == nil || (phy = ctlr->mii->curphy) == nil)
 			break;
-		if(miistatus(ctlr->mii) < 0)
+		if(miistatus(phy) < 0)
 			goto enable;
-
-		phy = ctlr->mii->curphy;
 		ilock(&ctlr->clock);
 		if(phy->fd)
 			ctlr->cr |= Fdx;
--- a/sys/src/9/pc/ethervt6105m.c
+++ b/sys/src/9/pc/ethervt6105m.c
@@ -482,7 +482,7 @@
 		for(i = 0; i < NMiiPhyr; i++){
 			if(i && ((i & 0x07) == 0))
 				p = seprint(p, e, "\n       ");
-			r = miimir(ctlr->mii, i);
+			r = miimir(ctlr->mii->curphy, i);
 			p = seprint(p, e, " %4.4uX", r);
 		}
 		p = seprint(p, e, "\n");
@@ -546,12 +546,10 @@
 	while(waserror())
 		;
 	for(;;){
-		if(ctlr->mii == nil || ctlr->mii->curphy == nil)
+		if(ctlr->mii == nil || (phy = ctlr->mii->curphy) == nil)
 			break;
-		if(miistatus(ctlr->mii) < 0)
+		if(miistatus(phy) < 0)
 			goto enable;
-
-		phy = ctlr->mii->curphy;
 		ilock(&ctlr->clock);
 		csr16w(ctlr, Cr, ctlr->cr & ~(Txon|Rxon));
 		if(phy->fd)
@@ -679,7 +677,7 @@
 	 * Wait for link to be ready.
 	 */
 	for(timeo = 0; timeo < 350; timeo++){
-		if(miistatus(ctlr->mii) == 0)
+		if(miistatus(ctlr->mii->curphy) == 0)
 			break;
 		tsleep(&up->sleep, return0, 0, 10);
 	}
@@ -1065,11 +1063,10 @@
 		return -1;
 	}
 //	print("oui %X phyno %d\n", phy->oui, phy->phyno);
-	USED(phy);
 
-	if(miistatus(ctlr->mii) < 0){
-//		miireset(ctlr->mii);
-		miiane(ctlr->mii, ~0, ~0, ~0);
+	if(miistatus(phy) < 0){
+//		miireset(phy);
+		miiane(phy, ~0, ~0, ~0);
 	}
 
 	return 0;
--- a/sys/src/9/port/ethermii.c
+++ b/sys/src/9/port/ethermii.c
@@ -10,12 +10,12 @@
 
 #include "ethermii.h"
 
-int
-mii(Mii* mii, int mask)
+uint
+mii(Mii* mii, uint mask)
 {
-	MiiPhy *miiphy;
-	int bit, oui, phyno, rmask;
-	u32int id;
+	MiiPhy *phy;
+	int oui, phyno;
+	uint bit, rmask, id;
 
 	/*
 	 * Probe through mii for PHYs in mask;
@@ -25,7 +25,7 @@
 	 */
 	rmask = 0;
 	for(phyno = 0; phyno < NMiiPhy; phyno++){
-		bit = 1<<phyno;
+		bit = 1U<<phyno;
 		if(!(mask & bit))
 			continue;
 		if(mii->mask & bit){
@@ -40,21 +40,21 @@
 		if(oui == 0xFFFFF || oui == 0)
 			continue;
 
-		if((miiphy = malloc(sizeof(MiiPhy))) == nil)
+		if((phy = malloc(sizeof(MiiPhy))) == nil)
 			continue;
 
-		miiphy->mii = mii;
-		miiphy->id = id;
-		miiphy->oui = oui;
-		miiphy->phyno = phyno;
+		phy->mii = mii;
+		phy->id = id;
+		phy->oui = oui;
+		phy->phyno = phyno;
 
-		miiphy->anar = ~0;
-		miiphy->fc = ~0;
-		miiphy->mscr = ~0;
+		phy->anar = ~0;
+		phy->fc = ~0;
+		phy->mscr = ~0;
 
-		mii->phy[phyno] = miiphy;
+		mii->phy[phyno] = phy;
 		if(mii->curphy == nil)
-			mii->curphy = miiphy;
+			mii->curphy = phy;
 		mii->mask |= bit;
 		mii->nphy++;
 
@@ -64,33 +64,35 @@
 }
 
 int
-miimir(Mii* mii, int r)
+miimir(MiiPhy *phy, int r)
 {
-	if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
+	Mii *mii;
+
+	if(phy == nil || (mii = phy->mii) == nil || mii->ctlr == nil)
 		return -1;
-	return mii->mir(mii, mii->curphy->phyno, r);
+	return mii->mir(mii, phy->phyno, r & 0x1F);
 }
 
 int
-miimiw(Mii* mii, int r, int data)
+miimiw(MiiPhy *phy, int r, int data)
 {
-	if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
+	Mii *mii;
+
+	if(phy == nil || (mii = phy->mii) == nil || mii->ctlr == nil)
 		return -1;
-	return mii->miw(mii, mii->curphy->phyno, r, data);
+	return mii->miw(mii, phy->phyno, r & 0x1F, data & 0xFFFF);
 }
 
 int
-miireset(Mii* mii)
+miireset(MiiPhy *phy)
 {
 	int bmcr;
 
-	if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
-		return -1;
-	bmcr = mii->mir(mii, mii->curphy->phyno, Bmcr);
+	bmcr = miimir(phy, Bmcr);
 	if(bmcr == -1)
 		return -1;
 	bmcr |= BmcrR;
-	mii->miw(mii, mii->curphy->phyno, Bmcr, bmcr);
+	miimiw(phy, Bmcr, bmcr);
 	microdelay(1);
 
 	return 0;
@@ -97,15 +99,11 @@
 }
 
 int
-miiane(Mii* mii, int a, int p, int e)
+miiane(MiiPhy *phy, int a, int p, int e)
 {
-	int anar, bmsr, mscr, r, phyno;
+	int anar, bmsr, mscr, r;
 
-	if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
-		return -1;
-	phyno = mii->curphy->phyno;
-
-	bmsr = mii->mir(mii, phyno, Bmsr);
+	bmsr = miimir(phy, Bmsr);
 	if(bmsr == -1)
 		return -1;
 	if(!(bmsr & BmsrAna))
@@ -113,10 +111,10 @@
 
 	if(a != ~0)
 		anar = (AnaTXFD|AnaTXHD|Ana10FD|Ana10HD) & a;
-	else if(mii->curphy->anar != ~0)
-		anar = mii->curphy->anar;
+	else if(phy->anar != ~0)
+		anar = phy->anar;
 	else{
-		anar = mii->mir(mii, phyno, Anar);
+		anar = miimir(phy, Anar);
 		if(anar == -1)
 			return -1;
 		anar &= ~(AnaAP|AnaP|AnaT4|AnaTXFD|AnaTXHD|Ana10FD|Ana10HD);
@@ -129,25 +127,25 @@
 		if(bmsr & Bmsr100TXFD)
 			anar |= AnaTXFD;
 	}
-	mii->curphy->anar = anar;
+	phy->anar = anar;
 
 	if(p != ~0)
 		anar |= (AnaAP|AnaP) & p;
-	else if(mii->curphy->fc != ~0)
-		anar |= mii->curphy->fc;
-	mii->curphy->fc = (AnaAP|AnaP) & anar;
+	else if(phy->fc != ~0)
+		anar |= phy->fc;
+	phy->fc = (AnaAP|AnaP) & anar;
 
 	if(bmsr & BmsrEs){
-		mscr = mii->mir(mii, phyno, Mscr);
+		mscr = miimir(phy, Mscr);
 		if(mscr == -1)
 			return -1;
 		mscr &= ~(Mscr1000TFD|Mscr1000THD);
 		if(e != ~0)
 			mscr |= (Mscr1000TFD|Mscr1000THD) & e;
-		else if(mii->curphy->mscr != ~0)
-			mscr = mii->curphy->mscr;
+		else if(phy->mscr != ~0)
+			mscr = phy->mscr;
 		else{
-			r = mii->mir(mii, phyno, Esr);
+			r = miimir(phy, Esr);
 			if(r == -1)
 				return -1;
 			if(r & Esr1000THD)
@@ -155,18 +153,18 @@
 			if(r & Esr1000TFD)
 				mscr |= Mscr1000TFD;
 		}
-		mii->curphy->mscr = mscr;
-		mii->miw(mii, phyno, Mscr, mscr);
+		phy->mscr = mscr;
+		miimiw(phy, Mscr, mscr);
 	}
-	if(mii->miw(mii, phyno, Anar, anar) == -1)
+	if(miimiw(phy, Anar, anar) == -1)
 		return -1;
 
-	r = mii->mir(mii, phyno, Bmcr);
+	r = miimir(phy, Bmcr);
 	if(r == -1)
 		return -1;
 	if(!(r & BmcrR)){
 		r |= BmcrAne|BmcrRan;
-		mii->miw(mii, phyno, Bmcr, r);
+		miimiw(phy, Bmcr, r);
 	}
 
 	return 0;
@@ -173,21 +171,15 @@
 }
 
 int
-miistatus(Mii* mii)
+miistatus(MiiPhy* phy)
 {
-	MiiPhy *phy;
-	int anlpar, bmsr, p, r, phyno;
-
-	if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
-		return -1;
-	phy = mii->curphy;
-	phyno = phy->phyno;
-
+	int anlpar, bmsr, p, r;
+	
 	/*
 	 * Check Auto-Negotiation is complete and link is up.
 	 * (Read status twice as the Ls bit is sticky).
 	 */
-	bmsr = mii->mir(mii, phyno, Bmsr);
+	bmsr = miimir(phy, Bmsr);
 	if(bmsr == -1)
 		return -1;
 	if(!(bmsr & (BmsrAnc|BmsrAna))) {
@@ -195,7 +187,7 @@
 		return -1;
 	}
 
-	bmsr = mii->mir(mii, phyno, Bmsr);
+	bmsr = miimir(phy, Bmsr);
 	if(bmsr == -1)
 		return -1;
 	if(!(bmsr & BmsrLs)){
@@ -206,7 +198,7 @@
 
 	phy->speed = phy->fd = phy->rfc = phy->tfc = 0;
 	if(phy->mscr){
-		r = mii->mir(mii, phyno, Mssr);
+		r = miimir(phy, Mssr);
 		if(r == -1)
 			return -1;
 		if((phy->mscr & Mscr1000TFD) && (r & Mssr1000TFD)){
@@ -217,7 +209,7 @@
 			phy->speed = 1000;
 	}
 
-	anlpar = mii->mir(mii, phyno, Anlpar);
+	anlpar = miimir(phy, Anlpar);
 	if(anlpar == -1)
 		return -1;
 	if(phy->speed == 0){
@@ -257,27 +249,27 @@
 }
 
 int
-miimmdr(Mii* mii, int a, int r)
+miimmdr(MiiPhy *phy, int a, int r)
 {
 	a &= 0x1F;
-	if(miimiw(mii, Mmdctrl, a) == -1)
+	if(miimiw(phy, Mmdctrl, a) == -1)
 		return -1;
-	if(miimiw(mii, Mmddata, r) == -1)
+	if(miimiw(phy, Mmddata, r) == -1)
 		return -1;
-	if(miimiw(mii, Mmdctrl, a | 0x4000) == -1)
+	if(miimiw(phy, Mmdctrl, a | 0x4000) == -1)
 		return -1;
-	return miimir(mii, Mmddata);
+	return miimir(phy, Mmddata);
 }
 
 int
-miimmdw(Mii* mii, int a, int r, int data)
+miimmdw(MiiPhy *phy, int a, int r, int data)
 {
 	a &= 0x1F;
-	if(miimiw(mii, Mmdctrl, a) == -1)
+	if(miimiw(phy, Mmdctrl, a) == -1)
 		return -1;
-	if(miimiw(mii, Mmddata, r) == -1)
+	if(miimiw(phy, Mmddata, r) == -1)
 		return -1;
-	if(miimiw(mii, Mmdctrl, a | 0x4000) == -1)
+	if(miimiw(phy, Mmdctrl, a | 0x4000) == -1)
 		return -1;
-	return miimiw(mii, Mmddata, data);
+	return miimiw(phy, Mmddata, data);
 }
--- a/sys/src/9/port/ethermii.h
+++ b/sys/src/9/port/ethermii.h
@@ -83,9 +83,8 @@
 };
 
 typedef struct Mii {
-	Lock;
 	int	nphy;
-	int	mask;
+	uint	mask;
 	MiiPhy*	phy[NMiiPhy];
 	MiiPhy*	curphy;
 
@@ -96,7 +95,7 @@
 
 typedef struct MiiPhy {
 	Mii*	mii;
-	u32int	id;
+	uint	id;
 	int	oui;
 	int	phyno;
 
@@ -111,12 +110,11 @@
 	int	tfc;
 };
 
-extern int mii(Mii*, int);
-extern int miiane(Mii*, int, int, int);
-extern int miimir(Mii*, int);
-extern int miimiw(Mii*, int, int);
-extern int miireset(Mii*);
-extern int miistatus(Mii*);
-
-extern int miimmdr(Mii*, int, int);
-extern int miimmdw(Mii*, int, int, int);
+extern uint mii(Mii*, uint);
+extern int miiane(MiiPhy*, int, int, int);
+extern int miimir(MiiPhy*, int);
+extern int miimiw(MiiPhy*, int, int);
+extern int miireset(MiiPhy*);
+extern int miistatus(MiiPhy*);
+extern int miimmdr(MiiPhy*, int, int);
+extern int miimmdw(MiiPhy*, int, int, int);
--- a/sys/src/9/teg2/ether8169.c
+++ b/sys/src/9/teg2/ether8169.c
@@ -444,7 +444,7 @@
 	print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 		phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 
-	miiane(ctlr->mii, ~0, ~0, ~0);
+	miiane(phy, ~0, ~0, ~0);
 	iunlock(&ctlr->reglock);
 
 	return 0;
@@ -610,7 +610,7 @@
 		for(i = 0; i < NMiiPhyr; i++){
 			if(i && ((i & 0x07) == 0))
 				p = seprint(p, e, "\n       ");
-			r = miimir(ctlr->mii, i);
+			r = miimir(ctlr->mii->curphy, i);
 			p = seprint(p, e, " %4.4ux", r);
 		}
 		p = seprint(p, e, "\n");
@@ -1221,7 +1221,7 @@
 
 	s = spllo();
 	/* Don't wait long for link to be ready. */
-	for(timeo = 0; timeo < 50 && miistatus(ctlr->mii) != 0; timeo++)
+	for(timeo = 0; timeo < 50 && miistatus(ctlr->mii->curphy) != 0; timeo++)
 //		tsleep(&up->sleep, return0, 0, 100); /* fewer miistatus msgs */
 		delay(100);
 
--- a/sys/src/9/teg2/mkfile
+++ b/sys/src/9/teg2/mkfile
@@ -132,7 +132,7 @@
 arch.$O clock.$O fpiarm.$O main.$O mmu.$O screen.$O sdscsi.$O syscall.$O \
 	trap.$O: /$objtype/include/ureg.h
 
-archtegra.$O devether.$0 ether9221.$O: ../port/etherif.h ../port/netif.h
+ether8169.$O: ../port/etherif.h ../port/netif.h ../port/ethermii.h
 archtegra.$O devflash.$O flashtegra.$O flashigep.$O: ../port/flashif.h
 ecc.$O flashtegra.$O flashigep.$O: ../port/nandecc.h io.h
 l.$O lexception.$O lproc.$O mmu.$O rebootcode.$O: arm.s mem.h
-- 
⑨