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ref: 605c0df143e172cff18162738ea142a2268e6aab
parent: b5344401da6ab27d87a5b6e6defc65d73dfdf31e
author: mia soweli <mia@soweli.net>
date: Sun Aug 10 14:58:19 EDT 2025 

vl: LL operand order and scheduling

LL should use AT&T syntax. LL and SC must be known to sched() so they
are not re-ordered. introduce a clumsy special case for SC because it
both reads from and writes to it's first register argument.


--- a/sys/src/cmd/vl/asm.c
+++ b/sys/src/cmd/vl/asm.c
@@ -1253,6 +1253,23 @@
 			v = p->cond->pc;
 		o1 = v;
 		break;
+
+
+	case 47:	/* sc r, soreg */
+		r = p->to.reg;
+		if(r == NREG)
+			r = o->param;
+		v = regoff(&p->to);
+		o1 = OP_IRR(opirr(p->as), v, r, p->from.reg);
+		break;
+
+	case 48:	/* ll soreg, r */
+		r = p->from.reg;
+		if(r == NREG)
+			r = o->param;
+		v = regoff(&p->from);
+		o1 = OP_IRR(opirr(p->as), v, r, p->to.reg);
+		break;
 	}
 	if(aflag)
 		return o1;
@@ -1472,8 +1489,8 @@
 	case AADDV:		return SP(3,0);
 	case AADDVU:		return SP(3,1);
 
-	case ALL:		return SP(6,0);
-	case ASC:		return SP(7,0);
+	case ALL:	return SP(6,0);
+	case ASC:	return SP(7,0);
 	}
 	diag("bad irr %d", a);
 	return 0;
--- a/sys/src/cmd/vl/optab.c
+++ b/sys/src/cmd/vl/optab.c
@@ -228,8 +228,8 @@
 	{ ACASE,	C_REG,	C_NONE,	C_NONE,		 45, 28, 0 },
 	{ ABCASE,	C_LCON,	C_NONE,	C_LBRA,		 46, 4, 0 },
 
-	{ ALL,		C_REG,	C_NONE,	C_SOREG,	 7, 4, REGZERO },
-	{ ASC,		C_REG,	C_NONE,	C_SOREG,	 7, 4, REGZERO },
+	{ ASC,		C_REG,	C_NONE,	C_SOREG,	 47, 4, 0 },
+	{ ALL,		C_SOREG,	C_NONE,	C_REG,	 48, 4, 0 },
 
 	{ AXXX,		C_NONE,	C_NONE,	C_NONE,		 0, 4, 0 },
 };
--- a/sys/src/cmd/vl/sched.c
+++ b/sys/src/cmd/vl/sched.c
@@ -341,6 +341,12 @@
 				print("botch %P\n", p);
 		}
 		break;
+
+	case ASC:
+	case ALL:
+		sz = 4;
+		ld = 1;
+		break;
 	}
 
 /*
@@ -516,6 +522,10 @@
 		s->used.ireg |= 1<<REGSB;
 		break;
 	case C_REG:
+		/* special case -- SC writes result to p->from.reg */
+		if (p->as == ASC)
+			s->set.ireg |= 1<<p->from.reg;
+
 		s->used.ireg |= 1<<p->from.reg;
 		break;
 	case C_FREG:
-- 
⑨