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ref: bf9c8472bf7e1218c420a2fb81b0abddb8221077
parent: d88192a6a501f15178d4c5f8cad4043968e38067
author: mia soweli <mia@soweli.net>
date: Mon Jul 28 17:57:42 EDT 2025 

7[al]: implement atomic register loads properly

these were not correct. 7l knew the opcodes, but they
were not in the optab and were not encoded correctly.
STLR and STLXR also have different arity since STLXR also
returns a status.

i have also dropped atomic load and store register pair
operations since they are wrong and we would need to
deal with the four operand STLXP.


--- a/sys/src/cmd/7a/lex.c
+++ b/sys/src/cmd/7a/lex.c
@@ -484,11 +484,10 @@
 	"SMSUBL",	LTYPEM,	ASMSUBL,
 	"SMULH",	LTYPE1,	ASMULH,
 	"SMULL",	LTYPE1,	ASMULL,
-	"STLR",	LSTXR,	ASTLR,
-	"STLRB",	LSTXR,	ASTLRB,
-	"STLRH",	LSTXR,	ASTLRH,
-	"STLRW",	LSTXR,	ASTLRW,
-	"STLXP",	LSTXR,	ASTLXP,
+	"STLR",	LTYPE3,	ASTLR,
+	"STLRB",	LTYPE3,	ASTLRB,
+	"STLRH",	LTYPE3,	ASTLRH,
+	"STLRW",	LTYPE3,	ASTLRW,
 	"STLXR",	LSTXR,	ASTLXR,
 	"STLXRB",	LSTXR,	ASTLXRB,
 	"STLXRH",	LSTXR,	ASTLXRH,
@@ -496,8 +495,6 @@
 	"STXR",	LSTXR,	ASTXR,
 	"STXRB",	LSTXR,	ASTXRB,
 	"STXRH",	LSTXR,	ASTXRH,
-	"STXP",	LSTXR,	ASTXP,
-	"STXPW",	LSTXR,	ASTXPW,
 	"STXRW",	LSTXR,	ASTXRW,
 	"SUB",	LTYPE1,	ASUB,
 	"SUBS",	LTYPE1,	ASUBS,
@@ -549,11 +546,6 @@
 	"LDARB",	LTYPE3,	ALDARB,
 	"LDARH",	LTYPE3,	ALDARH,
 	"LDARW",	LTYPE3,	ALDARW,
-
-	"LDXP",	LTYPE3,	ALDXP,
-	"LDXPW",	LTYPE3,	ALDXPW,
-	"LDAXP",	LTYPE3,	ALDAXP,
-	"LDAXPW",	LTYPE3,	ALDAXPW,
 
 	"LDAXR",	LTYPE3,	ALDAXR,
 	"LDAXRB",	LTYPE3,	ALDAXRB,
--- a/sys/src/cmd/7l/asmout.c
+++ b/sys/src/cmd/7l/asmout.c
@@ -805,12 +805,12 @@
 
 	case 59:	/* stxr */
 		o1 = opstore(p->as);
-		o1 |= p->reg << 16;
-		if(p->from3.type != D_NONE)
-			o1 |= p->from3.reg<<10;
-		else
-			o1 |= 0x1F<<10;
+		o1 |= 0x1F<<10;
 		o1 |= p->to.reg<<5;
+		if(p->reg != NREG)
+			o1 |= p->reg<<16;
+		else
+			o1 |= 0x1F<<16;
 		o1 |= p->from.reg;
 		break;
 
--- a/sys/src/cmd/7l/optab.c
+++ b/sys/src/cmd/7l/optab.c
@@ -463,15 +463,13 @@
 	{ ADMB,		C_LCON,	C_NONE, 	C_NONE,		51, 4, 0 },
 	{ AHINT,		C_LCON,	C_NONE,	C_NONE,		52, 4, 0 },
 
+	{ ALDAR,		C_ZOREG,	C_NONE,	C_REG,		58, 4, 0 },
 	{ ALDXR,		C_ZOREG,	C_NONE,	C_REG,		58, 4, 0 },
 	{ ALDAXR,		C_ZOREG,	C_NONE, C_REG,		58, 4, 0 },
-	{ ALDXP,		C_ZOREG,	C_REG,	C_REG,		58, 4, 0 },
-	{ ALDAXP,		C_ZOREG,	C_REG,	C_REG,		58, 4, 0 },
 
+	{ ASTLR,		C_REG,	C_NONE,	C_ZOREG,		59, 4, 0 },
 	{ ASTXR,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
 	{ ASTLXR,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
-	{ ASTXP,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
-	{ ASTLXP,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
 
 	{ AAESD,	C_VREG,	C_NONE,	C_VREG,	29, 4, 0 },
 	{ ASHA1C,	C_VREG,	C_REG,	C_VREG,	1, 4, 0 },
--- a/sys/src/cmd/7l/span.c
+++ b/sys/src/cmd/7l/span.c
@@ -1348,6 +1348,11 @@
 		case AMSR:
 			break;
 
+		case ALDAR:
+			oprange[ALDARW] = t;
+			oprange[ALDARH] = t;
+			oprange[ALDARB] = t;
+			break;
 		case ALDXR:
 			oprange[ALDXRW] = t;
 			oprange[ALDXRH] = t;
@@ -1363,6 +1368,11 @@
 			break;
 		case ALDAXP:
 			oprange[ALDAXPW] = t;
+			break;
+		case ASTLR:
+			oprange[ASTLRW] = t;
+			oprange[ASTLRH] = t;
+			oprange[ASTLRB] = t;
 			break;
 		case ASTXR:
 			oprange[ASTXRW] = t;
-- 
⑨