ref: e0e889fb69a6d4d3f2332244ef4f79f900a66d84
dir: /dat.h/
/* SMP Timer modes */
#define TIMER_MODE(lvt) (((lvt) >> 17) & 0x3)
#define MODE_ONESHOT 0
#define MODE_PERIODIC 1
#define MODE_DEADLINE 2
#define BACKSTOP_NS 50000000LL /* 10ms */
extern void dprint(char *fmt, ...);
extern char *vmx_segprefix;
#define MOUSE_PKT_BUF_SIZE 256
typedef struct HpetTimer HpetTimer;
struct HpetTimer {
u64int cfg;
u64int cmp;
u64int period; /* For periodic mode */
int active;
};
typedef struct Hpet Hpet;
struct Hpet {
Lock lock;
u64int cfg;
u64int status;
u64int counter_offset; /* Counter value when HPET was enabled/disabled */
uvlong time_at_enable; /* nsec() when HPET was enabled */
int enabled;
HpetTimer timer[3];
};
extern Hpet *hpet;
extern int mousepipe[2];
typedef struct UART UART;
struct UART {
Lock lk;
u8int ier, fcr, lcr, lsr, mcr, scr, dll, dlh;
u8int rbr, tbr;
enum {
UARTTXIRQ = 2,
UARTRXIRQ = 1,
} irq;
int infd, outfd;
Channel *inch, *outch;
};
extern UART *uart; /* pointer to shared memory */
/* I8042 keyboard/mouse controller - in shared memory */
typedef struct I8042 I8042;
struct I8042 {
Lock lk;
u8int cfg, stat, oport;
int cmd;
u16int buf;
u8int mouseactive;
};
extern I8042 *i8042;
#define KBD_BUF_SIZE 4096
/* Shared keyboard buffer */
typedef struct KbdShared KbdShared;
struct KbdShared {
Lock lk;
uchar buf[KBD_BUF_SIZE];
uvlong r, w;
};
extern KbdShared *kbdshared;
extern int kbdpipe[2];
#define UART_BUF_SIZE 4096
/* Shared UART RX buffer */
typedef struct UartShared UartShared;
struct UartShared {
Lock lk;
uchar buf[UART_BUF_SIZE];
uvlong r, w;
};
#define MOUSE_BUF_SIZE 256
/* Shared Mouse buffer for SMP */
typedef struct MouseShared MouseShared;
struct MouseShared {
Lock lk;
Lock packetlk;
struct {
short dx, dy; /* relative movement */
short dz; /* scroll wheel delta */
uchar buttons; /* button state */
uchar valid; /* entry is valid */
} buf[MOUSE_BUF_SIZE];
uvlong r, w; /* read and write indices */
};
extern MouseShared *mouseshared;
extern UartShared *uartshared[2];
extern int uartpipe[2][2];
extern int uarttxpipe[2][2];
extern int (*edev[16])(char *);
extern char *edevt[16];
extern char *edevaux[16];
extern int edevn;
typedef struct PCIDev PCIDev;
typedef struct PCICap PCICap;
typedef struct PCIBar PCIBar;
typedef struct Region Region;
typedef struct VmxNotif VmxNotif;
struct VmxNotif {
void (*f)(void *);
void *arg;
};
/* SMP Structures */
typedef struct LApic LApic;
typedef struct IOApic IOApic;
typedef struct IpiQueue IpiQueue;
extern int irqactive;
enum {
VMRUNNING,
VMHALT,
VMDEAD,
};
extern int state;
extern int debug;
enum {
BY2PG = 4096
};
#define RPC "pc"
#define RSP "sp"
#define RAX "ax"
#define RBX "bx"
#define RCX "cx"
#define RDX "dx"
#define RBP "bp"
#define RSI "si"
#define RDI "di"
#define R8 "r8"
#define R9 "r9"
#define R10 "r10"
#define R11 "r11"
#define R12 "r12"
#define R13 "r13"
#define R14 "r14"
#define R15 "r15"
#define RFLAGS "flags"
enum {
MMIORD = 0,
MMIOWRP = 1,
MMIOWR = 2,
};
struct Region {
uintptr start, end;
enum {
REGALLOC = 1,
REGR = 2,
REGW = 4,
REGX = 8,
REGRWX = REGR|REGW|REGX,
REGRX = REGR|REGX,
REGFREE = 1<<8,
REGRES = 2<<8,
} type;
char *segname;
uvlong segoff;
void *v, *ve;
Region *next;
int (*mmio)(uintptr, void *, int, int);
};
extern Region *mmap;
#define BDF(b,d,f) ((b)<<16&0xff0000|(d)<<11&0xf800|(f)<<8&0x700)
struct PCIBar {
PCIDev *d;
u8int type;
u32int addr, length;
PCIBar *busnext, *busprev;
u32int (*io)(int, u16int, u32int, int, void *);
void *aux;
};
enum {
BARIO = 1,
BARMEM32 = 0,
BARMEM64 = 4,
BARPREF = 8,
};
struct PCIDev {
u32int bdf, viddid, clrev, subid;
u16int ctrl;
u8int irqno, irqactive;
PCIBar bar[6];
PCIDev *next;
PCICap *cap;
u8int capalloc;
int sharedidx;
u32int cache_gen;
};
struct PCICap {
PCIDev *dev;
u8int length;
u8int addr;
u32int (*read)(PCICap *, u8int);
void (*write)(PCICap *, u8int, u32int, u32int);
PCICap *next;
};
enum {
IRQLTOGGLE = -1,
IRQLLOHI = -2,
NOERRC = -1,
};
typedef struct VgaMode VgaMode;
struct VgaMode {
u16int no;
int w, h, hbytes, sz;
u32int chan;
VgaMode *next;
};
extern void (*kconfig)(void);
enum {
SEGCS,
SEGDS,
SEGES,
SEGFS,
SEGGS,
SEGSS,
SEGMAX,
};
enum {
ACCR,
ACCW,
ACCX,
ACCSAFE = 0x100,
};
typedef struct TLB TLB;
struct TLB {
int asz, seg, acc;
uintptr start, end;
uintptr pabase;
Region *reg;
uchar *base;
};
/* SMP */
extern uint curcpuid;
#define MAXVCPU 8
extern uint nvcpu;
struct LApic {
u32int id;
u32int lvt_timer;
u32int timer_initial;
u32int timer_current;
u32int timer_divide;
vlong timer_deadline;
int timer_active;
uvlong tsc_deadline;
int tsc_deadline_armed;
};
struct IOApic {
Lock lock;
u32int reg_sel[16];
u32int id;
u64int redir[24];
uvlong tsc_base;
int cpu1_ready;
int cpu1_go;
u32int irq_pending;
u32int ldr[MAXVCPU];
u32int irq_level;
};
struct IpiQueue {
Lock lock[MAXVCPU];
struct {
u32int pending[8];
int wake;
} cpu[MAXVCPU];
int pids[MAXVCPU];
Lock sync_lock;
struct {
uvlong sync_tsc;
int sync_child_ready;
int sync_parent_ready;
int sync_round;
int sync_done;
} sync[MAXVCPU];
int wakefds[MAXVCPU];
int hltfs[MAXVCPU];
/* Store the write-end FDs here for clarity */
};
extern vlong cached_tscoff;
#define MAXPCIDEV 16
typedef struct PciShared PciShared;
struct PciShared {
Lock lock;
u32int cfgaddr;
struct {
u32int bdf;
u16int ctrl;
u8int irqno;
u8int irqactive;
u32int bar_addr[6];
} dev[MAXPCIDEV];
int ndev;
u32int generation;
};
typedef struct VIONotify VIONotify;
struct VIONotify {
int fd[2];
int pid;
};
extern VIONotify vionotify;
typedef struct VIOShared VIOShared;
struct VIOShared {
u8int data[32768];
uintptr alloc;
u8int isrstat;
int devpipes[8][2];
int ndevpipes;
void *blkdevs[8]; /* ADD: VIODev pointers for block devices */
int nblkdevs; /* ADD */
void *netdevs[8]; /* ADD: VIODev pointers for net devices */
int nnetdevs; /* ADD */
};
extern VIOShared *vioshared;
/* VGA shared state for SMP cursor synchronization */
typedef struct VgaShared VgaShared;
struct VgaShared {
Lock lk;
u8int crtc[0x18]; /* CRTC registers - includes cursor position */
};
extern VgaShared *vgashared;
typedef struct IPIQueue IPIQueue;
extern IpiQueue *ipiqueue;
/* Timer source identifiers */
enum {
TIMER_PIT = 0,
TIMER_RTC,
TIMER_HPET0,
TIMER_HPET1,
TIMER_HPET2,
TIMER_LAPIC,
TIMER_DEADLINE,
TIMER_MAX
};
/* Unified timer state */
typedef struct TimerQueue TimerQueue;
struct TimerQueue {
Lock lock;
vlong deadline[TIMER_MAX]; /* Deadline in nanoseconds, 0 = inactive */
vlong armed; /* Currently armed deadline */
};
/* PIT channel structure */
typedef struct PITChannel PITChannel;
struct PITChannel {
u8int mode;
u8int bcd;
u8int access;
u8int state;
u16int count, reload;
int latch;
enum { READLO, READHI, READLATLO, READLATHI } readstate;
u8int writestate;
vlong lastnsec;
u8int output;
};
/* PIT shared state - allocated via vioalloc() */
typedef struct PitShared PitShared;
struct PitShared {
Lock lock;
PITChannel ch[3];
u8int port61;
};
/* RTC shared state - allocated via vioalloc() */
typedef struct RtcShared RtcShared;
struct RtcShared {
Lock lock;
uchar cmos[0x30];
vlong rtcnext;
int cmosinit;
};